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1/29 november 2004 m69aw048b 32 mbit (2m x16) 3v asynchronous psram features summary supply voltage: 2.7 to 3.3v access times: 70ns low standby current: 100a deep power-down current: 10a byte control: ub /lb programmable partial array compatible with standard lpsram tri-state common i/o 8 word page access capability: 18ns wide operating temperature ?t a = ?30 to +85c power-down modes ? deep power-down ? 4 mbit partial array refresh ? 8 mbit partial array refresh ? 16 mbit partial array refresh figure 1. package fbga tfbga48 (zb) 6x8 mm
m69aw048b 2/29 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip enable (e1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 chip enable (e2 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 upper byte enable (ub ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 lower byte enable (lb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v cc supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 vss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 description of power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power-down program sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. power-down program sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. power-down configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. power-down configuration addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3/29 m69aw048b table 9. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. output enable controlled, read mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. ub /lb controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10.page address and chip enable controlled, read mode ac waveforms . . . . . . . . . . . . 16 figure 11.random and page address controlled, read mode ac waveforms . . . . . . . . . . . . . . . 17 table 12. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 12.chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13.write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14.write enable and ub /lb controlled, write ac waveforms 1 . . . . . . . . . . . . . . . . . . . . . 20 figure 15.write enable and ub /lb controlled, write ac waveforms 2 . . . . . . . . . . . . . . . . . . . . . 20 figure 16.write enable and lb /ub controlled, write ac waveforms 3 . . . . . . . . . . . . . . . . . . . . . 21 figure 17.write enable and lb /ub controlled, write ac waveforms 4 . . . . . . . . . . . . . . . . . . . . . 21 figure 18.chip enable controlled, read followed by write mode ac waveforms . . . . . . . . . . . . 22 figure 19.e1 , w , g controlled, read and write mode ac waveforms . . . . . . . . . . . . . . . . . . . . . 22 figure 20.output enable and write enable controlled, read and write mode ac waveforms . . . 23 figure 21.output enable, write enable and ub/lb controlled, read and write mode ac waveforms 23 table 13. standby/power-down mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 22.power down program ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23.power-down mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24.power-up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25.standby mode entry ac waveforms, after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 26.tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package outline, bottom view . . . . 26 table 14. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data. . . . . . . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m69aw048b 4/29 summary description the m69aw048b is a 32 mbit (33,554,432 bit) cmos memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7v to 3.3v supply voltage range. m69aw048b is a member of stmicroelectronics psram memory family. these devices are manu- factured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. however, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard asynchronous sram interface. the internal control logic of the m69aw048b han- dles the periodic refresh cycle, automatically, and without user involvement. write cycles can be performed on a single byte by using upper byte enable (ub ) and lower byte en- able (lb ). the device can be put into standby mode using chip enable (e1 ) or in power-down mode by us- ing chip enable (e2). the device features various kinds of power-down modes for power saving as a user configurable op- tion: the partial array refresh (par) performs a limited refresh of the part of the psram array (4 mbits, 8 mbits, 16mbits) that contains essential data. deep power-down mode: this mode achieves a very low current consumption by halting all the internal activities. since the refresh circuitry is halted, the duration of the power- down should be less than the maximum period for refresh. figure 2. logic diagram table 1. signal names ai05844c 21 a0-a20 w dq0-dq15 v cc m69aw048b g 16 e1 ub lb v ss e2 a0-a20 address input dq0-dq15 data input/output e1 , e2 chip enable, power down g output enable w write enable ub upper byte enable lb lower byte enable v cc supply voltage v ss ground nc not connected (no internal connection)
5/29 m69aw048b figure 3. tfbga connections (top view through package) ai07242 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 a20 a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 a19 ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc nc v ss dq6 a16
m69aw048b 6/29 signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a20). the address inputs select the cells in the memory array to access dur- ing read and write operations. data inputs/outputs (dq8-dq15). the upper byte data inputs/outputs carry the data to or from the upper part of the selected address during a write or read operation, when upper byte enable (ub ) is driven low. data inputs/outputs (dq0-dq7). the lower byte data inputs/outputs carry the data to or from the lower part of the selected address during a write or read operation, when lower byte enable (lb ) is driven low. chip enable (e1 ). when asserted (low), the chip enable, e1 , activates the memory state ma- chine, address buffers and decoders, allowing read and write operations to be performed. when de-asserted (high), all other pins are ignored, and the device is put, automatically, in low-power standby mode. chip enable (e2). the chip enable, e2, puts the device in power-down mode (deep power-down, par and standby) when it is driven low. one of these, deep power-down mode, is the lowest power mode. output enable (g ). the output enable, g , pro- vides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common i/o data bus. write enable (w ). the write enable, w , controls the bus write operation of the memory?s com- mand interface. upper byte enable (ub ). the upper byte en- able, ub , gates the data on the upper byte data inputs/outputs (dq8-dq15) to or from the upper part of the selected address during a write or read operation. lower byte enable (lb ). the lower byte en- able, lb , gates the data on the lower byte data inputs/outputs (dq0-dq7) to or from the lower part of the selected address during a write or read operation. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, write, etc.) and for driving the refresh logic, even when the device is not being accessed. v ss ground. the v ss ground is the reference for all voltage measurements.
7/29 m69aw048b figure 4. block diagram ai07221b dynamic memory array row decoder column decoder control logic e1 refresh controller arbitration logic internal clock generator input/output buffer address ub e2 g w lb power controller v cc v ss address dq0-dq7 dq8-dq15
m69aw048b 8/29 operation operational modes are determined by device con- trol inputs w , e1 , e2, lb and ub as summarized in the operating modes table (see table 2., operating modes ). power-up sequence because the internal control logic of the m69aw048b needs to be initialized, the following power-up procedure must be followed before the memory is used: ? apply power and wait for v cc to stabilize, ? wait 300s while driving both chip enable signals (e1 and e2) high. see also figure 24. for details on the power-up ac waveforms. read mode the device is in read mode when: ? write enable (w ) is high and ? output enable (g ) low and ? the two chip enable signals are asserted (e1 is low, and e2 is high). the time taken to enter read mode (t elqv , t glqv or t blqv ) depends on which of the above signals was the last to reach the appropriate level. data out (dq15-dq0) may be indeterminate dur- ing t elqx , t glqx and t blqx but data will always be valid during t avqv . see figures 7 , 8 , 9 , 10 and 11 and table 11., read mode ac characteristics , for details of when the outputs become valid. write mode the device is in write mode when ? write enable (w ) is low and ? chip enable (e1 ) is low and e2 is high ? at least one of upper byte enable (ub) and lower byte enable (lb) is low. the write cycle begins just after the event (the fall- ing edge) that causes the last of these conditions to become true (t avwl or t avel or t avbl ). the write cycle is terminated by the rising edge of write enable (w ) or chip enable (e1 ), whichever occurs first. if the device is in write mode (chip enable (e1 ) is low, output enable (g ) is low, upper byte en- able (ub ) and/or lower byte enable (lb ) is low, then write enable (w ) will return the outputs to high impedance within t whdz of its rising edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t d- vwh before the rising edge of write enable (w ), or for t dveh before the rising edge of chip enable (e1 ), whichever occurs first, and remain valid for t bhdz, t whdz , t ehdz . see figures 12 , 13 , 14 , 15 , 16 and 17 and table 12., write mode ac characteristics , for details of when the outputs become valid. standby mode the device is in standby mode when: ? chip enable (e1 )ishigh and ? chip enable (e2) is high the input/output buffers and the decoding/control logic are switched off, but the dynamic array con- tinues to be refreshed. in this mode, the memory current consumption, i sb , is reduced, and the data remains valid. see figures 17 and table 13., standby/power- down mode ac characteristics , for details of when the outputs become valid. power-down modes description of power-down modes. the m69aw048b has four power-down modes, deep power-down, 4 mbit partial array refresh, 8 mbit partial array refresh, and 16 mbit partial array refresh (see table 4. and figure 22. ). these can be entered using a series of read and write operations. each mode has following fea- tures. the default state is deep power-down and it is the lowest power consumption but all data will be lost once e2 is brought low for power-down. no sequence is required to put the device in deep power-down mode after power-up. the device is in one of the power-down modes when: ? chip enable (e2) is low all the device logic is switched off and all internal operations are suspended. this gives the lowest power consumption. in this operating mode, no re- fresh is performed, and data is lost if the duration is longer than 10ns. this mode is useful for those applications where the data contents are no longer needed, and can be lost, but where reduced cur- rent consumption is of major importance. power-down program sequence. the power- down program sequence is used to program the power-down configuration. it requires a total of six read and write operations, with specific ad- dresses and data. between each read or write op- eration the device must be in standby mode. table 4. shows the sequence. in the first cycle, the byte at the highest memory address (msb) is read. in the second and third cycles, the data (rda) read by first cycle are written back. if the third cycle is written into a different address, the sequence is aborted, and the data written by the third cycle is valid as in a normal write operation. in the fourth and fifth cycles, the power-down configuration data is written. the data of the fourth cycle must be
9/29 m69aw048b set to ?0000h?, and the data of the fifth cycle is the power-down configuration data (see table 5., power-down configuration data ). if the fourth cycle is written into a different address, the se- quence is aborted. in the last cycle, a read is made from the specific power-down configuration ad- dress (see table 6., power-down configuration addresses ). the power-down configuration data and address must correspond, otherwise the se- quence is aborted. when this sequence is performed to take the de- vice from one par mode to another, the write data may be lost. so, if a par mode is used, this se- quence should be performed prior to any normal read or write operations. table 2. operating modes note: x = v ih or v il . 1. should not be kept in this logic condition for a period longer than 1s. 2. power-down mode can be entered from standby state and all dq pins are in high-z state. the power-down current and data re- tention depend on the selection of power-down programming. 3. g can be v il during the write operation if the following conditions are satisfied: a. write pulse is initiated by e1 (e1 controlled write timing), or cycle time of the previous operation cycle is satisfied; b. g stays v il during the entire write cycle. table 3. power-down modes operation e1 e2 w g lb ub dq0-dq7 dq8-dq15 power standby (deselected) v ih v ih x x x x hi-z hi-z standby (i sb ) power-down (2) x v il x x x x hi-z hi-z power-down (i ccpd, i ccp4, i ccp8, i ccp16 ) no read (1) v il v ih v ih v il v ih v ih hi-z hi-z output disable lower byte read (1) v il v ih v ih v il v il v ih data output hi-z active (i cc ) lower byte write (1) v il v ih v il v ih v il v ih data input hi-z active (i cc ) no write v il v ih v il v ih v ih v ih hi-z hi-z output disable upper byte read (1) v il v ih v ih v il v ih v il hi-z data output active (i cc ) upper byte write (1) v il v ih v il v ih v ih v il hi-z data input active (i cc ) word read (1) v il v ih v ih v il v il v il data output data output active (i cc ) word write (1) v il v ih v il v ih (3) v il v il data input data input active (i cc ) mode data retention retention address deep power-down (default) no n/a 4mb par 4 mbit 00000h ? 3ffffh 8mb par 8 mbit 00000h ? 7ffffh 16mb par 16 mbit 00000h ? fffffh
m69aw048b 10/29 table 4. power-down program sequence note: 1. pdc power-down configuration. table 5. power-down configuration data table 6. power-down configuration addresses cycle # operation address data 1st read 1fffffh (msb) read data (rda) 2nd write 1fffffh rda 3rd write 1fffffh rda 4th write 1fffffh 0000h 5th write 1fffffh pdc data (1) 6th read pdc address (1) read data (rdb) power-down modes power-down configuration data dq15?dq9 dq8-dq2 dq1 dq0 deep power-down (default) 0011 4mb par 0 0 1 0 8mb par 0 0 0 1 16mb par 0000 power-down modes power-down configuration addresses a20 a19 a18?a0 binary deep power-down (default) 1 1 1 1fffffh 4mb par 0 1 1 0fffffh 8mb par 1 0 1 17ffffh 16mb par 0 0 1 07ffffh
11/29 m69aw048b maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 7. absolute maximum ratings symbol parameter min max unit i o output current ?50 50 ma t a ambient operating temperature ?30 85 c t stg storage temperature ?55 125 c v cc core supply voltage ?0.5 3.6 v v io input or output voltage ?0.5 3.6 v
m69aw048b 12/29 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 8., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 8. operating and ac measurement conditions note: 1. all voltages are referenced to v ss . 2. the input transition time used in ac measurements is 5ns. for other input transition times, see table 8. figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter m69aw048b unit 70 min max v cc supply voltage 1 2.7 3.3 v ambient operating temperature ?30 85 c load capacitance (c l ) 50 pf output circuit protection resistance (r 1 ) 50 ? input pulse voltages 0 v cc v input and output timing ref. voltages v cc /2 v output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc v input transition time 2 (t ) between v il and v ih 5ns ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai07222c v cc /2 out c l includes jig capacitance device under test c l r 1
13/29 m69aw048b table 9. capacitance table 10. dc characteristics note: 1. maximum dc voltage on input and i/o pins is v cc +0.2v. during voltage transitions, input may positive overshoot to v cc + 1.0v for a period of up to 5ns. 2. minimum dc voltage on input or i/o pins is ?0.3v. during voltage transitions, input may positive overshoot to v ss + 1.0v for a period of up to 5ns. symbol parameter test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 5pf c out output capacitance v out = 0v 8pf symbol parameter test condition min max unit i cc1 v cc active current v cc = 3.3v, v in = v ih or v il , e1 = v il and e2 = v ih , i out = 0ma t rc / t wc = minimum 30 ma i cc2 t rc / t wc = 1 s 3ma i cc3 v cc page read current v cc = 3.3v, v in = v ih or v il , e1 = v il and e2 = v ih , i out = 0ma, t prc = min. 10 ma i ccpd v cc power down current v cc = 3.3v, v in = v ih or v il , e2 0.2v deep power- down 10 a i ccp4 4 mb par 40 a i ccp8 8 mb par 50 a i ccp16 16 mb par 65 a i li input leakage current 0v v in v cc ?1 1 a i lo output leakage current 0v v out v cc ?1 1 a i sb standby supply current cmos v cc = 3.3v, v in 0.2v or v in v cc ?0.2v, e1 = e2 v cc ?0.2v 100 a v ih (1) input high voltage 0.8v cc v cc + 0.2 v v il (2) input low voltage ?0.3 0.2v cc v v oh output high voltage v cc = 2.7v, i oh = ?0.5ma 2.4 v v ol output low voltage i ol = 1ma 0.4 v
m69aw048b 14/29 table 11. read mode ac characteristics note: 1. maximum value is applicable if e1 is kept low without change of address input of a3 to a20. if needed by system operation, please contact your local st representative for relaxation of the 1000ns limitation. 2. address should not be changed within minimum read cycle time. 3. the output load 50pf with 50 ? termination to v cc *0.5 v. 4. the output load 5pf without any other load. 5. applicable to a3 to a20 when e1 is kept low. 6. applicable only to a0, a1 and a2 when e1 is kept low for the page address access. 7. in case page read cycle is continued with keeping e1 stays low, e1 must be brought to high within 4s. in other words, page read cycle must be closed within 4s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. minimum read cycle time and minimum page read cycle time must be satisfied. symbol alt. parameter m69aw048b unit min max t avax (1,2) t rc address valid time 70 1000 ns t avax2 (1,6,7) t prc page read cycle time 25 1000 ns t aveh2 (1,6,7) t prc page read cycle time 25 1000 ns t avel t asc address valid to chip enable low ?5 ns t avgl t aso address valid to output enable low 10 ns t avqv (3,5) t aa address valid to output valid 70 ns t avqv2 (3,6) t paa page address access time 18 ns t axav (5,8) t ax address invalid time 10 ns t axav2 (6,8) t axp page address invalid time 10 ns t axqx (3) t oh data hold from address change 3 ns t bhqx (3) t oh upper/lower byte enable high to output transition 3 ns t bhqz (4) t bhz upper/lower byte enable high to output hi-z 20 ns t blqv (3) t ba upper/lower byte enable low to output valid 30 ns t blqx (4) t blz upper/lower byte enable low to output transition 0 ns t ehax (9) t chah chip enable high to address invalid ?5 ns t ehel t cp chip enable high to chip enable low 15 ns t ehqx (3) t oh chip enable high to output transition 3 ns t ehqz (4) t chz chip enable high to output hi-z 20 ns t elax (1,2) t rc read cycle time 70 1000 ns t eleh (1,2) t rc read cycle time 70 1000 ns t elqv (3) t ce chip enable low to output valid 70 ns t elqx (4) t clz chip enable low to output transition 3 ns t ghax t ohah output enable high to address invalid ?5 ns t ghqx (3) t oh output data hold time 3 ns t ghqz (4) t ohz output enable high to output hi-z 20 ns t glqv (3) t oe output enable low to output valid 40 ns t glqx (4) t olz output enable low to output transition 0 ns
15/29 m69aw048b figure 7. read mode ac waveforms note: e2 = high, w = high. figure 8. output enable controlled, read mode ac waveforms note: write enable (w ) = high, e2 = high. a0-a20 e1 g lb, ub valid data output dq0-dq15 tavel telqv address valid valid tehax tavel tehel tehqz tghqz tbhqz tehqx tglqv tblqv tblqx tglqx telqx ai08986 teleh address valid address valid a0-a20 e1 g ub, lb data out data out dq0-dq15 tavax taxav tavax taxav taxav tavqv tavqv tglqv tglqx taxqx tghqz tghqx ai08987 tavgl tghax
m69aw048b 16/29 figure 9. ub /lb controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high. figure 10. page address and chip enable controlled, read mode ac waveforms note: write enable (w ) = high, e2 = high. a0-a20 address valid e1 lb ub dq0-dq7 dq8-dq15 valid data output valid data out valid data out tavax taxav taxav tavqv tblqv tblqx tbhqx tbhqz tblqx tblqv tblqv tblqx tbhqx tbhqz tbhqx tbhqz ai08990 low a20-a3 a2-a0 address valid address valid address valid e g lb, ub teleh tavel telax tavqv2 taxqx tavax2 taxqx taxqx tavqv2 tavqv2 tehqx tehqz tehax taveh telqx telqv address valid address valid ai08991 dq0-dq15 tavax2 tavax tavqv taxav2 taxav2 taxav2 valid data output valid data output valid data output valid data output
17/29 m69aw048b figure 11. random and page address controlled, read mode ac waveforms note: e2 = high. a20-a3 a2-a0 address valid e g lb, ub tavax taxav taxav2 tavax tavqv2 taxqx tavqv tglqx tblqx tglqv address valid address valid ai08992 dq0-dq15 address valid address valid address valid data out (normal access) data out (normal access) data out (page access) data out (page access) tavax taxav taxav tavax2 taxav2 tavax tavax2 tavqv tavqv2 low tblqv taxqx taxqx taxqx
m69aw048b 18/29 table 12. write mode ac characteristics note: 1. maximum value is applicable if e1 is kept low without any address change. if needed by system operation, please contact your local st representative for relaxation of the 1000ns limitation. 2. minimum value must be equal to or greater than the sum of write pulse ( t eleh , t wlbh or t blbh ) and write recovery time ( t ehax , t whax or t bhax ). 3. write pulse is defined from the falling edge of e1 , w , or lb /ub , whichever occurs last. 4. write recovery is defined from write pulse is defined from the rising edge of e1 , w , or lb /ub , whichever occurs first. 5. applicable to any address change when e1 stays low. 6. if g is low after minimum t ghel , the read cycle is initiated. in other words, g must be brought high within 5ns after e1 is brought low. once the read cycle is initiated, new write pulse should be input after minimum read cycle time is met. 7. if g is low after new address input, the read cycle is initiated. in other words, g must be brought high at the same time or before new address valid. once the read cycle is initiated, new writ e pulse should be input after minimum read cycle time is met. symbol alt. parameter m69aw048b unit min max t avax (1,2) t wc write cycle time 70 1000 ns t avbl (2) t as address valid to lb , ub low 0 ns t avel (2) t as address valid to chip enable low 0 ns t avwl (2) t as address valid to write enable low 0 ns t axav (5) t axw address invalid time for write 10 ns t bhax (4) t br lb , ub high to address transition 15 1000 ns t bhdz t dh lb , ub high to input high-z 0 ns t blbh (3) t bw lb , ub low to lb , ub high 45 ns t blbh2 t bwo lb , ub low to lb , ub high for page access 20 ns t blwh (3) t bw lb , ub low to write enable high 45 ns t dvbh t ds input valid to lb , ub high 20 ns t dveh t ds input valid to chip enable high 20 ns t dvwh t ds input valid to write enable high 20 ns t ehax (4) t wrc chip enable high to address transition 15 ns t ehdz t dh chip enable high to input high-z 0 ns t ehel t cp chip enable high to chip enable low 15 ns t elax (1,2) t wc write cycle time 70 1000 ns t eleh (3) t cw chip enable low to chip enable high 45 ns t ghav (7) t oes output enable high to address valid 0 ns t ghel (6) t ohcl output enable high to chip enable low ?5 ns t ghdz (4) t ohz output enable high to output hi-z 20 ns t whax (4) t wr write enable high to address transition 15 1000 ns t whdz t dh write enable high to input high-z 0 ns t wlbh (3) t wp write enable low to lb , ub high 45 ns t wlwh (3) t wp write enable low to write enable high 45 ns
19/29 m69aw048b figure 12. chip enable controlled, write ac waveforms note: e2 = high. figure 13. write enable controlled, write ac waveforms note: e2 = high. address valid a0-a20 e1 w lb, ub g dq0-dq15 telax teleh twlwh tavel tavel tehax tavwl tavwl twhax tbhax tblwh tavbl tavbl tghel valid data input tdveh tdvwh tdvbh tehdz twhdz tbhdz ai08993 address valid a0-a20 address valid address valid low tavax tavax tavwl twlwh tavwl twlwh tghav tghdz dq0-dq15 twhdx tdvwh twhdz tdvwh ai08994b e1 w lb, ub g valid data input valid data input twhax twhax taxav
m69aw048b 20/29 figure 14. write enable and ub /lb controlled, write ac waveforms 1 note: e2 = high. figure 15. write enable and ub /lb controlled, write ac waveforms 2 note: e2 = high. a0-a20 address valid address valid low taxav tavax tavax tavwl twlbh tbhax tavwl tbhax e1 w valid data input valid data input twlbh dq0-dq7 dq8-dq15 lb ub tdvbh tbhdz tdvbh tbhdz ai08995b a0-a20 address valid address valid low tavax tavax tavbl tblwh twhax tavbl twhax e1 w valid data input valid data input tblwh dq0-dq7 dq8-dq15 lb ub tdvwh twhdz tdvwh twhdz ai08996b taxav taxav
21/29 m69aw048b figure 16. write enable and lb /ub controlled, write ac waveforms 3 note: e2 = high. figure 17. write enable and lb /ub controlled, write ac waveforms 4 note: e2 = high. a0-a20 low tavax tavax tavbl tblbh tbhax tavbl tbhax e1 w valid data input valid data input tblbh dq0-dq7 dq8-dq15 lb ub tdvbh tbhdz tbvwh tbhdz ai08997b address valid address valid taxav taxav a0-a20 low tavax tavax tavbl tblbh e1 w valid data input valid data input dq0-dq7 dq8-dq15 lb tdvbh tbhdz ai08998b tbhax tdvbh tbhdz valid data input ub valid data input tavbl tblbh tbhax tdvbh tbhdz tblbh2 tblbh tblbh2 tblbh tdvbh tbhdz tavbl tbhax tavbl tbhax address valid address valid taxav taxav
m69aw048b 22/29 figure 18. chip enable controlled, read followed by write mode ac waveforms note: write address is valid from either e1 or w of last falling edge. figure 19. e1 , w , g controlled, read and write mode ac waveforms note: g can be low fixed in write operation under e1 control read-write-read operation. write address read address a0-a20 read data output write data input dq0-dq15 e1 w ub, lb g tehax (read) telax telax(read) tehax(read) tehax tavel tavel (read) teleh telqv tehel tehel tghel tehqx tehqz tehqx telqx tdveh tehdz ai08999b read data output write address read address a0-a20 read data output write data input dq0-dq15 e1 w ub, lb g tehax (read) telax telax(read) tehax(read) tavel tavel (read) teleh telqv tehel tehel tghel tehqx tehqz tghqx tglqx tdvwh twhdz ai09400b twhax twlwh tghqv read data output
23/29 m69aw048b figure 20. output enable and write enable controlled, read and write mode ac waveforms note: e1 can be tied to low for w and g controlled operation. when e1 is tied to low, output is exclusively controlled by g . figure 21. output enable, write enable and ub /lb controlled, read and write mode ac waveforms note: e1 can be tied to low for w and g controlled operation. when e1 is tied to low, output is exclusively controlled by g . write address read address a0-a20 data out data in dq0-dq15 e1 w ub, lb g twhax twlwh tghqx tghqz tghqx tglqx tdvwh twhdz ai09401b data out tglqv tavax tavax(read) tavqv tavgl tghqz low tavwl taxav taxav a0-a20 data out data in dq0-dq15 e1 w ub, lb g tbhax tblbh tbhqx tbhqz tbhqx tblqx tdvbh tbhdz ai09402b data out tblqv tavax tavax(read) tavbl tavqv tavgl tbhqz low write address read address taxav taxav
m69aw048b 24/29 table 13. standby/power-down mode ac characteristics note: 1. applicable also to power-up. 2. applicable when 4mb, 8mb and 16mb par mode is programmed 3. some data might be written into any address location if t ehwl (min) is not satisfied. 4. the input transition time (t ) at ac testing is 5ns as shown below. if actual t is longer than 5ns, it may violate ac specification of some timing parameters. figure 22. power down program ac waveforms note: 1. e2 = high. 2. all address inputs must be high from cycle 1 to cycle 5. 3. pdcadd stands for power-down configuration address. it must be compliant with the format specified in table 6 otherwise the data programmed during the power-down program sequence may be incorrect. 4. pdcdat stands for power-down configuration data. it must be compliant with the format specified in table 5 otherwise the data programmed during the power-down program sequence may be incorrect. 5. t ehel after the end of cycle 6, the power down program is completed and the device returns to normal operation. symbol alt. parameter m69aw048b unit min max t clex t csp e2 low setup time for power down entry 10 ns t exch t c2lp e2 low hold time after power down entry 70 ns t ehev (1) t chh e1 high hold time following e2 high after power- down exit (deep power-down mode only) 300 s t chel (2) t chhp e1 high hold time following e2 high after power- down exit (not in deep power-down mode) 1s t ehch t chs e1 high setup time following e2 high after power- down exit 0s t ehgl t chox e1 high to g invalid time for standby entry 10 ns t ehwl (3) t chwx e1 high to w invalid time for standby entry 10 ns t (4) t input transition time 1 25 ns ai07225c a0-a20 e1 w dq0-dq15 msb 2 g msb 2 msb 2 msb 2 msb 2 pdcadd 3 lb, ub taxav taxavl 4 tavax rda rda rda 00 pdcd 4 rdb cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6
25/29 m69aw048b figure 23. power-down mode ac waveforms figure 24. power-up mode ac waveforms figure 25. standby mode entry ac waveforms, after read note: e2 = high. e2 e1 ai09403 power-down entry power-down mode dq0-d15 tehch tclex texch tchel power-down exit hi-z ai09404 vdd tehel vddmin e1 e2 g e1 ai09405 w tehgl read active standby tehwl write active standby
m69aw048b 26/29 package mechanical figure 26. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package outline, bottom view note: drawing is not to scale. table 14. tfbga48 6x8mm - 6x8 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 ? ? 0.1476 ? ? ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.250 ? ? 0.2067 ? ? e 0.750 ? ? 0.0295 ? ? fd 1.125 ? ? 0.0443 ? ? fe 1.375 ? ? 0.0541 ? ? sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ? e1 e d1 d eb a2 a1 a bga-z26 ddd fd fe sd se e ball "a1"
27/29 m69aw048b part numbering table 15. ordering information scheme the notation used for the device number is as shown in table 15. . for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest stmi- croelectronics sales office. example: m69aw048 b l 70 zb 8 device type m69 = psram mode a = asynchronous operating voltage w = 2.7 to 3.3v array organization 048 = 32 mbit (2m x16) option 1 b = 2 chip enable option 2 l = low leakage speed class 70= 70 ns package zb = tfbga48, 0.75mm pitch operative temperature 8 = ?30 to 85 c
m69aw048b 28/29 revision history table 16. document revision history date version revision details 07-oct-2002 -01 first issue 10-mar-2003 2.0 document completely revised 9-mar-2004 3.0 data key and address key renamed power-down configuration data and power-down configuration address respectively. sleep mode renamed deep power-down mode. i ccs removed and i pd renamed i ccpd in table 10., dc characteristics . partial mode renamed partial array refresh. table 12. write mode ac characteristics : t ghdz added and note 2 updated. t ghqz changed to t ghdz in figure 13.write enable controlled, write ac waveforms . ac waveforms converted to st standard. 21-sep-2004 4.0 t elqz , t glqz , t blqz changed into t elqx , t glqx , t blqx in table 11., read mode ac characteristics . 15-nov-2004 5.0 v oh value updated in table 10., dc characteristics .
29/29 m69aw048b information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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